1. Field of the Invention
Generally, the present disclosure relates to the fabrication of sophisticated integrated circuits including transistor elements comprising highly capacitive gate structures on the basis of a high-k gate dielectric material of increased permittivity.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region substantially affects the performance of MOS transistors.
Presently, the vast majority of integrated circuits are based on silicon due to substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a base material of a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has continuously been decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current, while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although, generally, usage of high speed transistor elements having an extremely short channel may be substantially restricted to high speed signal paths, whereas transistor elements with a longer channel may be used for less critical signal paths, such as storage transistor elements, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may not be compatible with thermal design power requirements for performance driven circuits.
Therefore, replacing silicon dioxide based dielectrics as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide based gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. It has thus been suggested to replace silicon dioxide with high permittivity materials such as tantalum oxide (Ta2O5), with a k of approximately 25, strontium titanium oxide (SrTiO3), having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
Additionally, transistor performance may be increased by providing an appropriate conductive material for the gate electrode to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance based on the same thickness as a silicon dioxide based layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, the non-polysilicon material, such as titanium nitride and the like, in combination with other metals, may be formed so as to connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone. Since the threshold voltage of the transistors, which represents the voltage at which a conductive channel forms in the channel region, is significantly determined by the work function of the metal-containing gate material, an appropriate adjustment of the effective work function with respect to the conductivity type of the transistor under consideration has to be guaranteed.
Providing different metal species for adjusting the work function of the gate electrode structures for P-channel transistors and N-channel transistors at an early manufacturing stage may, however, be associated with a plurality of difficulties, which may stem from the fact that a complex patterning sequence may be required during the formation of the sophisticated high-k metal gate stack, which may result in a significant variability of the resulting work function and thus threshold of the completed transistor structures. For instance, during a corresponding manufacturing sequence, the high-k material may be exposed to oxygen, which may result in an increase of layer thickness and thus a reduction of the capacitive coupling. Moreover, a shift of the work function may be observed when forming appropriate work function metals in an early manufacturing stage, which is believed to be caused by a moderately high oxygen affinity of the metal species, in particular during high temperature processes which may typically be required for completing the transistor structures, for instance for forming drain and source regions and the like.
For this reason, in some approaches, the initial gate electrode stack may be provided with a high degree of compatibility with conventional polysilicon-based process strategies and the actual electrode metal and the final adjustment of the work function of the transistors may be accomplished in a very advanced manufacturing stage, i.e., after completing the basic transistor structure.
In a corresponding replacement gate approach, the polysilicon material acting as a sacrificial or placeholder material is removed after depositing at least a portion of the interlayer dielectric material by any appropriate etch techniques. Typically, the interlayer dielectric material may comprise stress-inducing dielectric layers in order to further enhance overall transistor performance. It is well known that a high strain component in the channel region of silicon-based transistors may result in a significant modification of the mobility of the charge carriers and thus of the overall conductivity of the channel region. For this reason, a stress-inducing dielectric material may be placed in close proximity to the transistors in order to provide a desired strain component in the channel regions. Since P-channel transistors and N-channel transistors may require a different type of strain component, the stress-inducing dielectric materials may be provided with a different internal stress level in order to selectively enhance performance of N-channel transistors and P-channel transistors, respectively. The selective provision of an appropriately stressed dielectric material may be accomplished on the basis of the so-called “dual stress liner” approach in which a sequence of deposition and removal processes in combination with an appropriate masking regime is applied in order to position, for instance, a tensile stressed dielectric material above an N-channel transistor and a compressively stressed dielectric material above a P-channel transistor. Frequently, the stress-inducing dielectric materials may be provided in the form of a silicon nitride material, which may be deposited on the basis of well-established process techniques so as to exhibit the desired internal stress level. On the other hand, the different internal stress level obtained by different process parameters of the plasma enhanced chemical vapor deposition (CVD) process may also result in different material characteristics, for instance with respect to the etch resistivity during the subsequent patterning of the interlayer dielectric material. In particular, during the exposure of the sacrificial gate material during the replacement gate approach, the different material characteristic of the stressed dielectric materials may result in a significant degree of process non-uniformity, as will be described in more detail with reference to FIGS. 1a-1b. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in a very advanced manufacturing stage. The semiconductor device 100 comprises a substrate 101 and a silicon-based semiconductor layer 102 formed above the substrate 101. Moreover, a first device region 110A and a second device region 110B may represent areas in and above the semiconductor layer 102 in which a plurality of circuit elements, such as transistors 150A, 150B, are provided. For example, the transistors 150A may represent P-channel transistors while the transistors 150B may represent N-channel transistors. The transistors 150A, 150B may be positioned within the device regions 110A, 110B in accordance with a specific design of the semiconductor device 100, which may strongly be dependent on process specifics of a replacement gate approach, as will be described later on in more detail. The transistors 150A, 150B may comprise a gate electrode structure 160 comprising a sophisticated material stack 161, which typically includes a high-k dielectric material, for instance one of the materials as specified above, in combination with a metal-containing cap material. Furthermore, the gate electrode structure 160 comprises a placeholder or sacrificial material 162 in the form of a silicon material, possibly in combination with a dielectric cap layer 163. As previously explained, in sophisticated applications, a gate length, i.e., a horizontal extension of the gate electrode structure 160, may be 50 nm and less. The gate electrode structure may have formed on sidewalls thereof an offset spacer element 151, such as a silicon nitride spacer, which may reliably protect sidewalls of sensitive materials in the layer 161. Moreover, a spacer structure 152 is typically provided, such as a silicon nitride spacer material, possibly in combination with an etch stop liner (not shown). Furthermore, the transistors 150A, 150B comprise drain and source regions 154 and a channel region 153, the conductivity of which is to be increased by inducing a certain strain component, as discussed above. Additionally, the drain and source regions 154 may comprise metal silicide regions 155. It should be appreciated that, for convenience, the configuration of the transistors 150A, 150B is illustrated identically for these devices, while, however, in an actual implementation, differences may exist, in particular with respect to the type of doping of the drain and source regions 154 and the channel region 153. Furthermore, in the manufacturing stage shown, the device 100 comprises an interlayer dielectric material or at least a portion thereof, as indicated by 170, which includes a first stress inducing layer 171A having an internal stress level so as to increase performance of the transistors 150A. Similarly, the interlayer dielectric material 170 comprises a second stress-inducing layer 171B having an internal stress level that is appropriate for increasing performance of the transistors 150B. Typically, the materials 171A, 171B may be comprised of silicon nitride of different material composition, for instance with respect to the contents of other species, such as hydrogen and the like. The interlayer dielectric material may comprise a dielectric material 172, such as silicon dioxide, as is frequently used as an efficient interlayer dielectric material.
The semiconductor device 100 may be formed on the basis of any well-established manufacturing strategy in accordance with a replacement gate approach. That is, after defining appropriate active regions for the device areas 110A, 110B by forming isolation structures (not shown), the gate electrode structures 160 are formed by depositing or otherwise forming the layer 161 in combination with the sacrificial silicon material 162 and the cap layer 163. If required, other materials, such as an anti-reflective coating (ARC) material, a hard mask material and the like, may be deposited. Next, the resulting layer stack is patterned by using advanced lithography and etch techniques, thereby obtaining the gate electrode structures 160 with the desired critical dimension. Thereafter, the spacer element 151 may be formed, followed by implantation of appropriate dopant species in combination with the formation of the spacer structure 152 in order to appropriately define the final dopant profile of the drain and source regions 154. After activating the dopant species, the metal silicide regions 155 are formed by applying well-established process techniques. Next, the layers 171A, 171B are formed by depositing a dielectric material, such as a silicon nitride material, having a desired stress level, partially removing the material and depositing a further silicon nitride material having the other type of internal stress. Thereafter, an unwanted portion of the second silicon nitride layer is removed, thereby providing the layers 171A, 171B selectively above the transistors 150A, 150B, respectively. Thereafter, the dielectric material 172 is deposited, thereby obtaining the configuration as shown in FIG. 1a. Thus, the basic transistor configuration is completed, whereas, however, the gate electrode structures 160 may still require an appropriate adaptation of the work function for the transistors 150A, 150B and the provision of a highly conductive metal-containing electrode material. For this purpose, the sacrificial polysilicon material 162 is to be exposed in order to enable an efficient removal thereof.
During the removal of a portion of the material 170 for exposing the polysilicon material 162, however, undue material erosion, also referred to as “dishing,” between the gate electrode structures 160 is to be avoided when applying advanced polishing techniques, since, during the subsequent replacement of the polysilicon material 162, a corresponding metal-containing material may remain between the electrode structures 160 and may result in enhanced leakage currents or complete failure of the structure.
FIG. 1b schematically illustrates the semiconductor device 100 during a corresponding removal process 103 during which the layer 172 may be planarized in an initial step, followed by a polishing step for removing material of the layers 171A, 171B and of the layer 172. During the removal process 103, the different material characteristics of the layer 171A, 171B caused by the difference in deposition parameters and thus internal stress level, and the removal of the material 172 provided in the form of a silicon dioxide material may result in different removal rates, thereby contributing to a pronounced non-uniformity. For example, dishing may occur between the gate electrode structures, as indicated by the dashed lines 173, wherein the degree of dishing 173 may even vary with respect to the regions 110A, 110B due to the different material characteristics of the layers 171A, 171B. Furthermore, the removal rate may significantly depend on the distribution of circuit features in the device regions 110A, 110B, that is, for instance, on the distribution of the gate electrode structures 160 and the size thereof, so that large polysilicon areas may suffer from a significant degree of over-polish in order to reliably expose the polysilicon material 162 in other device areas. Due to this pattern dependent removal behavior, frequently, a specifically designed layout is used in order to obtain a desired degree of uniformity across an entire die and also an entire substrate. However, a corresponding specific design may contribute to a very restricted flexibility in designing complex integrated circuits.
After the removal process 103, during which the polysilicon material 162 is exposed, an appropriate etch process may be performed in order to remove the polysilicon material 162 and appropriate metal-containing materials for the gate electrode structures 160 of the transistors 150A, 150B, respectively, are deposited in accordance with any appropriate manufacturing sequence.
In other conventional approaches, the restrictions with respect to circuit design and the like of the removal process 103 may be reduced by applying a “non-selective” plasma-based etch process in order to remove the material of the planarized layer 172 in combination with the layers 171A, 171B and the cap layers 163 (FIG. 1a). However, during the plasma-based etch process having the desired degree of non-selectivity, polymer components may deposit on and in the increasingly exposed polysilicon material 162, which may result in a certain contamination and thus non-uniformity during the subsequent process to be performed for removing the polysilicon material 162, in particular when very efficient wet chemical etch strategies are considered. Consequently, in this case, significant non-uniformities may be introduced due to significantly affecting the further processing when replacing the polysilicon material 162 with metal-containing electrode materials.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.